Device size scaling significantly increases the impact of parametric variability on design performances, especially for sensitive circuits. Monte Carlo (MC) simulation is a conventional methodology to statistically analyze the parametric yield under process variations. In traditional MC analysis, pseudo-random sampling (PRS) is used to generate input samples for simulation. Based on a pseudo-random numbers, small variations in one or more process parameters are selected, to define the process conditions, and a SPICE simulation of a device or circuit design is run, assuming that the process selected parameters are used. This is repeated for a large number of pseudo-random numbers (and corresponding process conditions). However, traditional MC analysis often requires several thousand SPICE simulations such that the iterative yield-aware design flow at circuit-level becomes impractical for large circuits.
The traditional PRS approach often requires huge amount of simulation time for accurate yield estimation for a single design. If the designer makes a design change, this large simulation time is repeated.